Studying LSI Tamper Resistance with Respect to Techniques Developed for Failure Analysis
نویسندگان
چکیده
Abstract: Tamper resistance of LSI chips against physical attacks is studied from the viewpoint of LSI failure analysis. Laying stress on the basic physical phenomena generated in LSI chips under operating conditions, we outline today’s failure analysis techniques with application to evaluating or testing tamper resistance of LSI chips. We give some results from our case study on inactivation of sensor circuits where emission microscopy plays an important roll. Finally we show an attempt to classify the security levels for LSI chips with respect to the required equipment and the required skills of attackers.
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